The present invention relates to a semiconductor integrated circuit device and a manufacturing technology of the same. More particularly, the present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
In the field of the semiconductor device, the number of power supplies mounted on one semiconductor chip has been increased in recent years. Therefore, a so-called two-level gate insulator process has been put into practical use, in which a gate insulating film with a small thickness and a gate insulating film with a large thickness are respectively formed on the same surface of a semiconductor chip.
In the standard process for the two-level gate insulator, a semiconductor substrate made of single crystal silicon (hereinafter, simply referred to as substrate) is first subjected to the wet oxidation to form a silicon oxide film on the surface thereof. Subsequently, the insulating film in a region where a thick gate insulating film is to be formed (first region) is covered with a photoresist film, and the insulating film in a region where a thin gate insulating film is to be formed (second region) is removed by the etching. By so doing, the substrate surface in the second region is exposed.
Next, after the removal of the photoresist film, the substrate is subjected to the wet oxidation again, thereby forming a thin gate insulating film on the substrate surface in the second region. At this time, since the insulating film in the first region is also grown and the thickness thereof is increased, a thick gate insulating film is formed in the first region.
Also, the two-level gate insulator process is disclosed in the gazette of Japanese Patent Application Laid-Open No. 2000-188338, in which a gate insulating film made of silicon oxide and a gate insulating film made of silicon nitride are respectively formed in the first region and the second region of a substrate.
In the process described in the gazette, a first silicon oxide film is formed on the substrate in the first and second regions. Thereafter, the first silicon oxide film in the first region is selectively removed by the etching to expose a semiconductor substrate surface in the first region. Next, after forming a silicon nitride film on the substrate in the first region and on the first silicon oxide film in the second region, the silicon nitride film and the first silicon oxide film in the second region are selectively removed to expose the substrate surface in the second region. Subsequently, the substrate is subjected to thermal oxidation to form a second silicon oxide film on the substrate surface in the second region. In this manner, a first gate insulating film made of silicon nitride is formed on the substrate surface in the first region, and a second gate insulating film made of silicon oxide is formed on the semiconductor substrate surface in the second region.
In the ongoing development for higher capacity DRAM, the reduction of the gate length and that of the pitch between gate electrodes in the MISFET (Metal Insulator Semiconductor Field Effect Transistor) that constitutes the memory cell have been carried out in order to achieve the scaling of the memory cell to the smaller size.
However, the simple reduction of the gate length in the MISFET that constitutes the memory cell causes the reduction of the threshold voltage, and resulting in the reduction of the operational reliability of the memory cell. Therefore, the method that the impurity concentration in the channel region is set high is commonly used as a method to keep the threshold voltage at a predetermined level or higher even if the gate length is reduced.
However, if the channel impurity concentration in the MISFET that constitutes the memory cell is increased, the field intensity at the interface between the source/drain region and the channel region is increased, and the leakage current at this interface is increased. Consequently, another problem that the refresh characteristics are reduced is caused.
Also, the method of forming the gate insulating film to have a large thickness is available as a method to keep the threshold voltage at a predetermined level or higher while keeping the channel impurity concentration of the MISFET that constitutes the memory cell at a low level. However, on the other hand, since it is necessary to reduce the thickness of the gate insulating film in proportion to the scaling of the MISFET in order to achieve the high performance and the low voltage operation of the MISFET, the gate insulating film of the MISFET that constitutes the peripheral circuit is needed to be thinner than the gate insulating film of the MISFET that constitutes the memory cell.
As described above, the introduction of the two-level gate insulator process has become inevitable also in the manufacture of a DRAM. However, in the conventional two-level gate insulator process in which the two kinds of gate insulating films each having different thicknesses are formed on the same substrate, the number of photomasks and that of manufacturing steps are increased. Therefore, if the two-level gate insulator process is introduced in the manufacturing process of the DRAM, the increase in the manufacturing cost of the DRAM is caused.
An object of the present invention is to provide a technique capable of realizing the two-level gate insulator process in the manufacture of the DRAM without increasing the number of manufacturing steps and that of the photomasks.
The above and other objects and novel characteristics of the present invention will be apparent from the description and the accompanying drawings of this specification.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
An aspect of the present invention is a semiconductor integrated circuit device, in which a plurality of first MISFETs each having a first gate electrode is formed in a first region of a main surface of a semiconductor substrate and a plurality of second MISFETs each having a second gate electrode is formed in a second region of the main surface of the semiconductor substrate, the second gate electrode having a gate length longer than that of the first gate electrode, wherein thickness of a gate insulating film formed just below a center of the first gate electrode is larger than that of the gate insulating film formed just below a center of the second gate electrode, and wherein thickness of a gate insulating film formed just below a sidewall portion of the first gate electrode is equal to that of the gate insulating film formed just below a sidewall portion of the second gate electrode.
Another aspect of the present invention is a method of manufacturing a semiconductor integrated circuit device, which comprises the steps of:
(a) forming a gate insulating film in first and second regions of a main surface of a semiconductor substrate;
(b) forming a conductive film on the gate insulating film;
(c) etching the conductive film to form a first gate electrode on the gate insulating film in the first region and a second gate electrode on the gate insulating film in the second region, the second gate electrode having a gate length longer than that of the first gate electrode;
(d) performing thermal treatment to the semiconductor substrate to make the gate insulating film formed just below the center of the first gate electrode thicker than the gate insulating film formed just below the center of the second gate electrode; and
(e) after the step (d), forming a first MISFET having the first gate electrode in the first region and forming a second MISFET having the second gate electrode in the second region.
Another aspect of the present invention is a method of manufacturing a semiconductor integrated circuit device, wherein a first gate electrode with a short gate length and a second gate electrode with a long gate length-are formed on a semiconductor substrate via a gate insulating film with a uniform thickness, and at the same time with the oxidation process to the semiconductor substrate in order to increase the thickness of the gate insulating film located at the edge portions of the first and second gate electrodes, the thickness of the gate insulating film located at the center of the first gate electrode is increased to be larger than that of the gate insulating film located at the center of the second gate electrode by taking advantage of the short gate length of the first gate electrode.
In this manner, it is possible to easily provide the two kinds of MISFETs having gate insulating films with different thicknesses without complicated manufacturing process. In addition, it is also possible to provide the MISFET having high threshold voltage without increasing the substrate concentration.